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FAST CMOS OCTAL TRANSCEIVER/ REGISTERS (3-STATE)
Integrated Device Technology, Inc.
IDT54/74FCT646T/AT/CT/DT - 2646T/AT/CT IDT54/74FCT648T/AT/CT IDT54/74FCT652T/AT/CT/DT - 2652T/AT/CT
FEATURES:
* Common features: - Low input and output leakage 1A (max.) - Extended commercial range of -40C to +85C - CMOS power levels - True TTL input and output compatibility - VOH = 3.3V (typ.) - VOL = 0.3V (typ.) - Meets or exceeds JEDEC standard 18 specifications - Product available in Radiation Tolerant and Radiation Enhanced versions - Military product compliant to MIL-STD-883, Class B and DESC listed (dual marked) - Available in DIP, SOIC, SSOP, QSOP, TSSOP, CERPACK and LCC packages * Features for FCT646T/648T/652T: - Std., A, C and D speed grades - High drive outputs (-15mA IOH, 64mA IOL) - Power off disable outputs permit "live insertion" * Features for FCT2646T/2652T: - Std., A, and C speed grades - Resistor outputs (-15mA IOH, 12mA IOL Com.) (-12mA IOH, 12mA IOL Mil.) - Reduced system switching noise
DESCRIPTION:
The FCT646T/FCT2646T/FCT648T/FCT652T/2652T consist of a bus transceiver with 3-state D-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. The FCT652T/FCT2652T utilize GAB and GBA signals to control the transceiver functions. The FCT646T/FCT2646T/ FCT648T utilize the enable control (G) and direction (DIR) pins to control the transceiver functions. SAB and SBA control pins are provided to select either realtime or stored data transfer. The circuitry used for select control will eliminate the typical decoding glitch that occurs in a multiplexer during the transition between stored and realtime data. A LOW input level selects real-time data and a HIGH selects stored data. Data on the A or B data bus, or both, can be stored in the internal D flip-flops by LOW-to-HIGH transitions at the appropriate clock pins (CPAB or CPBA), regardless of the select or enable control pins. The FCT26xxT have balanced drive outputs with current limiting resistors. This offers low ground bounce, minimal undershoot and controlled output fall times-reducing the need for external series terminating resistors. FCT2xxxT parts are plug-in replacements for FCTxxxT parts.
IDT54/74FCT652/2652 ONLY GBA GAB
FUNCTIONAL BLOCK DIAGRAM
IDT54/74FCT646/2646/648 ONLY G DIR CPBA SBA CPAB SAB
B REG 1 OF 8 CHANNELS 1D C1 646/2646/652/2652 ONLY
A1
A REG 1D C1
B1
646/2646/652/2652 ONLY
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2634 drw 01
TO 7 OTHER CHANNELS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(c)1996 Integrated Device Technology, Inc.
SEPTEMBER 1996
DSC-2634/9
6.20
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IDT54/74FCT646/2646/652/2652T/AT/CT/DT, 648T/AT/CT FAST CMOS OCTAL TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CPAB NC VCC
GND NC B8
A7
A8
B7
B6
CPAB SAB DIR A1 A2 A3 A4 A5 A6 A7 A8 GND
1 2 3 4 5 6 7 8 9 10 11 12
P24-1 D24-1 SO24-2 SO24-7* SO24-8 SO24-9* & E24-1
24 23 22 21 20 19 18 17 16 15 14 13
VCC CPBA SBA
DIR
G
FCT646/FCT2646T FCT648
A1 A2 A3 NC A4 A5 A6
5 6 7 8 9
4
SAB
INDEX
3 2 1 28 27 26 25 24 23 L28-1 22 21
CPBA SBA
PIN CONFIGURATIONS
G
B1 B2 NC B3 B4 B5
B1 B2 B3 B4 B5 B6 B7 B8
2634 drw 02
10 20 1112 13 14 15 16 17 1819
2634 drw 03
DIP/SOIC/SSOP/ QSOP/TSSOP/CERPACK TOP VIEW
* FCT646/2646T/AT/CT/DT only
LCC TOP VIEW
GAB
CPAB SAB GAB A1 A2 A3 A4 A5 A6 A7 A8 GND
1 2 3 4 5 6 7 8 9 10 11 12
P24-1 D24-1 SO24-2 SO24-7* SO24-8 & E24-1
24 23 22 21 20 19 18 17 16 15 14 13
VCC CPBA SBA
FCT652/FCT2652T
A1 A2 A3 NC A4 A5 A6 5 6 7 8
GBA
4
SAB
INDEX
B1 B2 B3 B4 B5 B6 B7 B8
2634 drw 04
3 2 1 28 27 26 25 24 23 L28-1
CPAB NC VCC
CPBA SBA
GBA
B1 B2 NC B3 B4 B5
2634 drw 05
22 21 9 10 20 19 11 12 13 14 15 16 17 18
GND NC A7 A8 B8 B7 B6
DIP/SOIC/SSOP/ QSOP/CERPACK TOP VIEW
* FCT652/2652T/AT/CT/DT only
LCC TOP VIEW
PIN DESCRIPTION
Pin Names A1 - A8 B1 - B8 CPAB, CPBA SAB, SBA GAB, GBA DIR, G Description Data Register A Inputs Data Register B Outputs Data Register B Inputs Data Register A Outputs Clock Pulse Inputs Output Data Source Select Inputs Output Enable Inputs (646/648) Output Enable Inputs (652)
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IDT54/74FCT646/2646/652/2652T/AT/CT/DT, 648T/AT/CT FAST CMOS OCTAL TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTION TABLE (646/648)
Inputs Data I/O(1) SAB X X X X L H SBA X X L H X X A1 - A8 Input Output Input B1 - B8 Input Input Output Operation or Function FCT646T/FCT2646T Isolation Store A and B Data Real-Time B Data to A Bus Stored B Data to A Bus Real-Time A Data to B Bus Stored A Data to B Bus FCT648T Isolation Store A and B Data Real-Time B Data to A Bus Stored B Data to A Bus Real-Time A Data to B Bus Stored A Data to B Bus
2634 tbl 02
G
H H L L L L
DIR X X L L H H
CPAB H or L X X X H or L
CPBA H or L X H or L X X
FUNCTION TABLE (652)
Inputs GAB L L X H L L L L H H H Data I/O SAB X X X X(2) X X X X L H H SBA X X X X X X(2) L H X X H A1 - A8 Input Input Input Unspecified(1) Output Output Input Output B1 - B8 Input Operation or Function FCT652T/FCT2652T Isolation Store A and B Data
GBA
H H H H X L L L H H L
CPAB H or L H or L X X X H or L H or L
CPBA H or L H or L X H or L X X H or L
Unspecified(1) Store A, Hold B Output Store A in Both Registers Input Input Input Output Output Hold A, Store B Store B in Both Registers Real-Time B Data to A Bus Stored B Data to A Bus Real-Time A Data to B Bus Stored A Data to B Bus Stored A Data to B Bus and Stored B Data to A Bus
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NOTES: 1. The data output functions may be enabled or disabled by various signals at the GAB or GBA inputs. Data input functions are always enabled, i.e. data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs. 2. Select control = L: clocks can occur simultaneously. Select control = H: clocks must be staggered in order to load both registers. H = HIGH, L = LOW, X = Don't Care, = LOW-to-HIGH transition. 3. A in B Register. 4. B in A Register.
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IDT54/74FCT646/2646/652/2652T/AT/CT/DT, 648T/AT/CT FAST CMOS OCTAL TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
BUS A
BUS B
BUS A
BUS B
GAB L 646/2646/ DIR 648 L 652/2652
GBA L G L
CPAB X CPAB X
CPBA X CPBA X
SAB X SAB X
SBA L SBA L
652/2652 646/2646/ 648
GAB H DIR H
GBA H G L
CPAB X CPAB X
CPBA X CPBA X
SAB L SAB L
SBA X SBA X
REAL-TIME TRANSFER BUS B TO A
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REAL-TIME TRANSFER BUS A TO B
2634 drw 07
BUS A
BUS B
BUS A
BUS B
652/2652
GAB X L L DIR H L X
GBA H X H G L L H
CPAB X CPAB X
CPBA X CPBA X
SAB X X X SAB X X X
SBA X X X SBA X X X
652/2652
GAB H
(1)
GBA L G L L
CPAB H or CPAB X H or
CPBA H or CPBA H or X
SAB H SAB X H
SBA H SBA H X
646/2646/ 648
646/2646/ 648
DIR L H
TRANSFER STORES DATA TO A AND/OR B
2634 drw 09
STORAGE FROM A AND/OR B
NOTE: 1. 646/2646/648 cannot transfer data to A bus and B bus simultaneously.
2634 drw 08
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IDT54/74FCT646/2646/652/2652T/AT/CT/DT, 648T/AT/CT FAST CMOS OCTAL TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description Max. VTERM(2) Terminal Voltage with Respect to -0.5 to +7.0 GND (3) Terminal Voltage with Respect to VTERM -0.5 to GND VCC +0.5 TSTG Storage Temperature -65 to +150 IOUT DC Output Current -60 to +120 Unit V V
CAPACITANCE (TA = +25C, f = 1.0MHz)
Symbol Parameter(1) CIN Input Capacitance COUT Output Capacitance Conditions VIN = 0V VOUT = 0V Typ. 6 8 Max. Unit 10 pF 12
pF
2634 lnk 05
C
mA
NOTE: 1. This parameter is measured at characterization but not tested.
2634 lnk 04 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed VCC by +0.5V unless otherwise noted. 2. Input and VCC terminals only. 3. Outputs and I/O terminals only.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Commercial: TA = -40C to +85C, VCC = 5.0V 5%; Military: TA = -55C to +125C, VCC = 5.0V 10%
Symbol VIH VIL II H II L IOZH IOZL II VIK VH ICC Parameter Input HIGH Level Input LOW Level Input HIGH Current(4) Input LOW Current (4) High Impedance Output Current (3-State Output pins) (4) VCC = Min., IIN = -18mA
--
Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max. VCC = Max. VI = 2.7V VI = 0.5V VO = 2.7V VO = 0.5V VCC = Max., VI = VCC (Max.)
Min. 2.0 -- -- -- -- -- -- -- -- --
Typ.(2) -- -- -- -- -- -- -- -0.7 200 0.01
Max. -- 0.8 1 1 1 1 1 -1.2 -- 1
Unit V V A A A V mV mA
2634 lnk 05
Input HIGH Current(4) Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current
VCC = Max., VIN = GND or VCC
OUTPUT DRIVE CHARACTERISTICS FOR FCT646T/648T/652T
Symbol VOH Parameter Output HIGH Voltage Test Conditions(1) VCC = Min. IOH = -6mA MIL. VIN = VIH or VIL IOH = -8mA COM'L. IOH = -12mA MIL. IOH = -15mA COM'L. VCC = Min. IOL = 48mA MIL. VIN = VIH or VIL IOL = 64mA COM'L. VCC = Max., VO = GND (3) VCC = 0V, VIN or VO 4.5V Min. 2.4 2.0 -- -60 -- Typ.(2) 3.3 3.0 0.3 -120 -- Max. -- -- 0.55 -225 1 Unit V V V mA A
2634 lnk 06
VOL IOS IOFF
Output LOW Voltage Short Circuit Current Input/Output Power Off Leakage(5)
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IDT54/74FCT646/2646/652/2652T/AT/CT/DT, 648T/AT/CT FAST CMOS OCTAL TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
OUTPUT DRIVE CHARACTERISTICS FOR FCT2646T/2652T
Symbol IODL IODH VOH VOL Parameter Output LOW Current Output HIGH Current Output HIGH Voltage Output LOW Voltage Test Conditions(1) VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V (3) VCC = 5V, VIN = VIH or V IL, VOUT = 1.5V (3) VCC = Min. VIN = VIH or VIL VCC = Min. VIN = VIH or VIL IOH = -12mA MIL. IOH = -15mA COM'L. IOL = 12mA Min. 16 -16 2.4 -- Typ.(2) 48 -48 3.3 0.3 Max. -- -- -- 0.50 Unit mA mA V V
2634 lnk 07
NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 5.0V, +25C ambient. 3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second. 4. The test limit for this parameter is 5A at TA = -55C. 5. This parameter is guaranteed but not tested.
POWER SUPPLY CHARACTERISTICS
Symbol ICC ICCD Parameter Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current (4) Test Conditions(1) VCC = Max. VIN = 3.4V(3) VCC = Max. Outputs Open GAB = GBA = GND or G = DIR = GND One Input Toggling 50% Duty Cycle VCC = Max. Outputs Open fCP = 10MHz 50% Duty Cycle GAB = GBA = GND or G = DIR = GND One Bit Toggling at fi = 5MHz 50% Duty Cycle VCC = Max. Outputs Open fCP = 10MHz 50% Duty Cycle GAB = GBA = GND or G = DIR = GND Eight Bits Toggling at fi = 2.5MHz 50% Duty Cycle Min. -- -- Typ.(2) 0.5 0.15 Max. 2.0 0.25 Unit mA mA/ MHz
VIN = VCC FCTxxxT VIN = GND FCT2xxxT
--
0.06
0.12
IC
Total Power Supply Current (6)
VIN = VCC FCTxxxT VIN = GND FCT2xxxT FCTxxxT VIN = 3.4 VIN = GND FCT2xxxT
-- -- --
1.5 0.6 2.0 1.1
3.5 2.2 5.5 4.2
mA
VIN = VCC FCTxxxT VIN = GND FCT2xxxT VIN = 3.4 FCTxxxT VIN = GND FCT2xxxT
-- -- -- --
3.8 1.5 6.0 3.8
7.3 (5) 4.0 (5) 16.3 (5) 13.0 (5)
NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fCP/2 + fiNi) ICC = Quiescent Current ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) fi = Input Frequency Ni = Number of Inputs at fi All currents are in milliamps and all frequencies are in megahertz.
2634 tbl 08
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IDT54/74FCT646/2646/652/2652T/AT/CT/DT, 648T/AT/CT FAST CMOS OCTAL TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
646/648/652T 2646/2652T Com'l. Mil. Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ tPLH tPHL tPLH tPHL tSU tH tW Parameter Propagation Delay Bus to Bus Output Enable Time, G, DIR to Bus (3) Output Disable Time, G, DIR to Bus (3) Propagation Delay Clock to Bus Propagation Delay SBA or SAB to Bus Set-up Time HIGH or LOW Bus to Clock Hold Time HIGH or LOW Bus to Clock Clock Pulse Width, HIGH or LOW Condition(1) CL = 50pF RL = 500
Min.(2) Max. Min.(2) Max.
646/648/652AT 2646/2652AT Com'l. Mil.
Min.(2) Max. Min.(2) Max.
2.0 2.0 2.0 2.0 2.0 4.0 2.0 6.0
9.0 14.0 9.0 9.0 11.0 -- -- --
2.0 2.0 2.0 2.0 2.0 4.5 2.0 6.0
11.0 15.0 11.0 10.0 12.0 -- -- --
2.0 2.0 2.0 2.0 2.0 2.0 1.5 5.0
6.3 9.8 6.3 6.3 7.7 -- -- --
2.0 2.0 2.0 2.0 2.0 2.0 1.5 5.0
7.7 10.5 7.7 7.0 8.4 -- -- --
Unit ns ns ns ns ns ns ns ns
2634 tbl 09
646/648/652CT 2646/2652CT Com'l. Mil. Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ tPLH tPHL tPLH tPHL tSU tH tW Parameter Propagation Delay Bus to Bus Output Enable Time, G, DIR to Bus (3) Output Disable Time, G, DIR to Bus (3) Propagation Delay Clock to Bus Propagation Delay SBA or SAB to Bus Set-up Time HIGH or LOW Bus to Clock Hold Time HIGH or LOW Bus to Clock Clock Pulse Width, HIGH or LOW(4) Condition(1) CL = 50pF RL = 500
Min.(2) Max. Min.(2) Max.
646/652DT Com'l. Mil.
Min.(2) Max. Min.(2) Max.
1.5 1.5 1.5 1.5 1.5 2.0 1.5 5.0
5.4 7.8 6.3 5.7 6.2 -- -- --
1.5 1.5 1.5 1.5 1.5 2.0 1.5 5.0
6.0 8.9 7.7 6.3 7.0 -- -- --
1.5 1.5 1.5 1.5 1.5 1.5 1.0 3.0
4.4 5.0 4.3 4.4 5.0 -- -- --
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
Unit ns ns ns ns ns ns ns ns
NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. GAB, GBA to Bus for 652. 4. This parameter is guaranteed but not tested.
2634 tbl 10
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IDT54/74FCT646/2646/652/2652T/AT/CT/DT, 648T/AT/CT FAST CMOS OCTAL TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS TEST CIRCUITS FOR ALL OUTPUTS
V CC 500 VIN Pulse Generator RT D.U.T. 50pF CL
2634 drw 10
SWITCH POSITION
Test
7.0V
Switch
Open Drain Disable Low Enable Low All Other Tests
Closed Open
VOUT
500
2634 lnk 11 DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tSU
tH
3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V
2634 drw 11
LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE
1.5V
tREM
1.5V
2634 drw 12
tSU
tH
PROPAGATION DELAY
3V 1.5V 0V VOH 1.5V VOL 3V 1.5V 0V
2634 drw 13
ENABLE AND DISABLE TIMES
ENABLE DISABLE 3V 1.5V tPZL OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH SWITCH CLOSED tPZH SWITCH OPEN 1.5V 0V 3.5V 1.5V tPHZ 0.3V VOH 0V
2634 drw 14
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL
CONTROL INPUT tPLZ
0V 3.5V 0.3V VOL
NOTES: 1. Diagram shown for input Control Enable-LOW and input Control DisableHIGH 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns
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IDT54/74FCT646/2646/652/2652T/AT/CT/DT, 648T/AT/CT FAST CMOS OCTAL TRANSCEIVER/REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT XX FCT X Temperature Family Range XXXX Device Type X Package X Process/ Temperature Range Blank B P D SO L E PY Q PG 646T 648T 652T 646AT 648AT 652AT 646CT 648CT 652CT 646DT 652DT Blank 2 54 74 Commercial MIL-STD-883, Class B Plastic DIP (P24-1) CERDIP (D24-1) Small Outline IC (SO24-2) Leadless Chip Carrier (L28-1) CERPACK (E24-1) Shrink Small Outline Package (SO24-7) Quarter-size Small Outline Package (SO24-8) Thin Shrink Small Outline Package (SO24-9) Non-inverting Octal Transceiver/Register Inverting Octal Transceiver/Register Inverting Octal Transceiver/Register Non-inverting Octal Transceiver/Register
High Drive Balanced Drive -55C to +125C -40C to +85C
2634 drw 15
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